Stacked mass storage flash memory package

ABSTRACT

A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates generally to packaged semiconductordevices. More particularly, the invention pertains to flash memorydevices having high memory density.

[0003] 2. State of the Art

[0004] The use of semiconductor integrated circuit (IC) chips iswidespread, in both commercial grade and specific high reliabilityapplications. Continuing progress in the manufacture of IC chips hasresulted in chips of greatly increased density, i.e. higher numbers ofdevices per footprint area of each chip. In addition, to produceincreasingly complex electronic components, it is necessary to include amuch greater number of IC chips on a substrate, e.g. circuit board. Onesolution to this dilemma is to form a stack of chips on a substrate,creating what is known in the art as a multi-chip package.

[0005] The state of the art in vertically stacked MCM devices isillustrated by representative prior art devices shown in drawing FIGS. 1through 11.

[0006] A representative example of a known multi-chip semi-conductorapparatus 10, prior to packaging, is shown in drawing FIG. 1.

[0007] A plurality of chips or dice 12A, 12B and 12C are mounted in apyramidal stack on a substrate 14. Each die is mounted with an adhesivematerial 16 to the next lower die or substrate, and is electricallyconnected to the metallized substrate 14 by bond wires 18 using knownwire bonding methods. Variants of this multi-chip configuration aredescribed in U.S. Pat. No. 5,422,435 to Takiar et al., Japan Patent62-8534(A) to Tsukahara and Japan Patent 3-165550(A) to Yashiro. In eachof these references, a pyramidal stack is formed of increasingly smallerchips or dice 12, in order to accommodate the placement of bond wires 18on peripheral portions of each die. This configuration is not generallyuseful where dice of equal dimensions are to be placed in a multi-chipmodule (MCM), such as in a memory device.

[0008] In drawing FIG. 2, a pyramidal stack of chips in device 10 isshown as described in U.S. Pat. No. 5,399,898 to Rostoker. In thesereferences, the dice comprise “flip-chips” with solder bumps or balls 20joined to conductive areas on the backside 22 of the underlying chip.

[0009] Depicted in drawing FIG. 3 is a MCM configuration 10 in which afirst die 12A is attached to a substrate 14 with adhesive 16, and iselectrically connected to the substrate with bond wires 18. A second die12B is stacked atop the first die and connected to it by solder balls20. The second die is smaller than the first die, in order to leaveaccess to the first die's conductive areas. This type of arrangement isdepicted in Japan Patent 56-158467(A) to Tsubouchi, and a variantthereof is described in Japan Patent 63-104343 to Kuranaga.

[0010] Depicted in drawing FIG. 4 is an MCM device 10 formed of dice 12Aand 12D mounted on opposite surfaces of a substrate 14. In this example,the substrate 14 is a lead frame, and the construction permits both ofthe dice to be connected to a metallization on one surface of the leadframe. This construction is described in U.S. Pat. No. 5,012,323 toFarnworth.

[0011] Each of the above stacking configurations requires that the dicebe of differing sizes. This is mandated by the need to leave the bondpads of each die unobstructed for wire attachment.

[0012] There have been various configurations of MCM packages in whichchips of equal dimensions are stacked. Several such configurations areshown in drawing FIGS. 5, 6, 7, 8, 9, 10 and 11 and described below.

[0013] In one MCM configuration shown in U.S. Pat. No. 5,973,403 to Warkand Japan Patent 5-13665(A) to Yamauchi, a flip-chip 12A is electricallybonded to a substrate 14 by posts, balls or other connectors 20, and asecond chip i.e. die 12B is attached back-to-back to the flip-chip (withan intervening insulation layer 24) and connected by wires 18 to thesubstrate. This particular MCM device 10 is illustrated in drawing FIG.5.

[0014] In another form, depicted in drawing FIG. 6, two chips 12A, 12Bare mounted on opposite sides of a substrate 14, with interveninginsulation layers 24. The dice 12A, 12B are shown with wire bonds 18.This general dice-to-substrate configuration with variants is picturedin U.S. Pat. No. 5,147,815 to Casto, U.S. Pat. No. 5,689,135 to Ball,and U.S. Pat. No. 5,899,705 to Akram.

[0015] An MCM apparatus 10 which combines various die configurationsalready described above in drawing FIGS. 1 through 6 is shown in U.S.Pat. No. 6,051,878 to Akram et al. The apparatus uses conductivecolumn-like structures to connect substrates which carry the dice.

[0016] As shown in drawing FIG. 7, an MCM device 10 described in U.S.Pat. No. 5,483,024 to Russell et al. has two identical dice 12A, 12Bwith central bond pads. The dice are sandwiched between and attached totwo lead frames 14A, 14B with discontinuous adhesive layers 16. The diceare joined by an intervening insulation layer 24. Bond wires 18 connecteach die to the corresponding lead frame.

[0017] In drawing FIG. 8, a stacked MCM device 10 is depicted inaccordance with the disclosure of U.S. Pat. No. 5,323,060 to Fogal etal. In this device, dice 12A, 12B, 12C, and 12D are verticallyalternated with adhesive layers 16A, 16B and 16C. The thickness of theadhesive layers is enhanced to be greater than the bond wire loopheight, so that bond wires 18 may be attached to the active surfaces ofthe dice, for connection to the substrate 14.

[0018] Described in U.S. Pat. No. 5,291,061 to Ball is a similar stackeddevice 10 in which the thickness of the adhesive layers 16A, 16B and 16Cis reduced, using a low-loop-profile wire-bonding operation.

[0019] As shown in drawing FIG. 9, a configuration generally shown inU.S. Pat. No. 5,399,898 to Rostoker uses an upper flip-chip die 12E tojoin dice 12A mounted on a substrate 14. The dice 12A are connected tosubstrate metallization with bond wires. Thus, the apparatus 10comprises three dice connected serially.

[0020] There are various forms of a MCM apparatus in which separateenclosed units are first formed and then stacked. Examples are describedin U.S. Pat. No. 5,434,745 to Shokrgozar et al. and U.S. Pat. No.5,128,831 to Fox, III et al. A typical stacked apparatus 10 of thisconstruction is depicted in drawing FIG. 10, showing three units. Eachunit comprises an intermediate substrate 14A with a metallized surface.A die 12A, 12B or 12C is mounted on the intermediate substrate 14A, andconnected to the metallization 30 by bond wires 18. A wall 32surrounding each die 12 encloses the die 12, wires 18, and metallization30. The various metallization leads extend to conductive columns 34within the wall 32, the latter connected to metallization 40 onsubstrate 14. An insulative cover 38 protects the upper unit and forms aprotective shell about the device.

[0021] In another MCM package design 10 shown in drawing FIG. 11, aplurality of dice 12A, 12B, . . . have bevelled edges 28 which permitthe bonding of wires to edge bond pads on the active surfaces 26. Thisdesign requires that the die thickness 36 be sufficiently great toaccommodate wire loop height in the bevelled regions. If the diethickness is insufficient, the thickness of adhesive layers 16 must beincreased. Thus, the device height will be increased. Also, the bevelleddie edges 28 are weak and subject to breakage.

[0022] In each of the above prior art configurations for forming MCMpackages containing a stack of identically configured dice, variouslimitations and/or problems exist as indicated above. A new packagedesign is needed in which a plurality of identical dice with bond padsalong one edge or two edges may be readily stacked for paralleloperation. The new design must provide a package requiring fewermanufacturing steps and providing high density with enhancedreliability.

BRIEF SUMMARY OF THE INVENTION

[0023] In accordance with the invention, a stacked multiple chip deviceis formed of two or more chips i.e. dice, in which bond pads are locatedin areas along one or two edges of the active surface of each die. Thedevice of the invention is particularly useful when configured to beformed of a stack of semiconductor dice which are substantially the sameor similar in shape, size and bond pad arrangement, although notnecessarily of identical shape, size and bond pad arrangement. Anexample of this die configuration is a mass memory storage device with arow or rows of bond pads along one edge of the semiconductor die.

[0024] In a device of this invention, the dice are arranged in a stackin which each individual semiconductor die being positionally offsetfrom the next lower semiconductor die, thus exposing the bond pads ofeach die for wire bonding or other conductor attachment. In someembodiments, a semiconductor die may overhang bond pads of an underlyingsemiconductor die, but the thickness of an intervening offsetsemiconductor die supporting the overhanging semiconductor die, togetherwith two thin adhesive layers, provides sufficient “headroom” toaccommodate the wire loop height. The thickness (Z-dimension) ofadhesive layers may be minimized to reduce overall device height. Wherebond pads are overhung by another die, wire bonding is successfullyaccomplished without the use of thick adhesive layers.

[0025] The substrate may be any body which supports the device,including for example, a circuit board, circuit card such as a multiplememory card, a lead frame or a tape automated bonding (TAB) tape. Thebond pads of each die are exposed for rapid precise bond wiring to thesubstrate. In one embodiment, the apparatus is formed as a single stackof dice connected to a substrate whose reverse surface is configured forsolder-ball bonding to another metallized surface.

[0026] In this invention, semiconductor dice having bond pads along oneedge only need not be offset from each other in more than one direction.Semiconductor dice configured with bond pads along two adjacent edgesare always offset from each other along two axes, i.e. in twodirections. The offset exposes bond pads of a lower die to permitconvenient wire bonding between each chip and a substrate.

[0027] Where the stack comprises more than two semiconductor dice, theoffset of each semiconductor die may be positive or negative along bothaxes. The stack may include a reversal in the direction of offset. Inthis case, the die underlying the die having an offset direction changemust also be rotated in orientation about a central Z-axis. The activesurface of the semiconductor die may be rotated to place the bond padsadjacent a different location of the substrate. Such rotation maycomprise 0, 90, 180 or 270 degrees in a clockwise or counter-clockwisedirection.

[0028] Packaging of the device may use conventional processes forenclosing the semiconductor dice and conductors in a plastic, metal orceramic encapsulant.

[0029] Some embodiments of the invention having up to four or moresemiconductor dice provide complete exposure of all bond pads.

[0030] Use of this design provides adequate space for wire-bonding thebond pads which underlie die edges of a higher semiconductor die,because the spacer consists not of a thick adhesive layer, but anintervening die or a piece of silicon or similar material substantiallythe same size as the semiconductor die. In some instances, inoperativesemiconductor die may be used in the stack between operativesemiconductor die located on either side thereof. The designs of thestack and the substrate are coordinated to provide an easily formeddevice which may for example have a high memory density, minimal height,short bond wires, small footprint, and high speed and responsiveness. Inone embodiment, the package is particularly useful as a high speedmulti-die mass storage flash memory device with a high memory density.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031]FIGS. 1 through 11 are side views of various prior artconfigurations of multi-chip modules (MCM);

[0032]FIG. 12 is an isometric view of an offset stacked multiple diedevice with a single offset in accordance with the invention;

[0033]FIG. 12A is an isometric view of an offset stacked multiple diedevice with a single offset, mounted on a lead frame, in accordance withthe invention;

[0034]FIG. 12B is an isometric view of an offset stacked multiple diedevice with a single offset die of smaller size, mounted on a leadframe, in accordance with the invention;

[0035]FIG. 12C is an isometric view of an offset stacked multiple diedevice with a single offset die of larger size, mounted on a lead frame,in accordance with the invention;

[0036]FIG. 13 is a side view of an offset stacked multiple die devicewith a single offset in accordance with the invention;

[0037]FIG. 14 is a plan view of an offset stacked multiple die devicewith a single offset in accordance with the invention;

[0038]FIG. 15 is a side view of another embodiment of an offset stackedmultiple die device in accordance with the invention;

[0039]FIG. 16 is a side view of a further embodiment of an offsetstacked multiple die device in accordance with the invention;

[0040]FIGS. 17 through 24 are simplified side views of various exemplaryembodiments of unencapsulated stacked multiple die devices havingdifferent configurations of one-axis die stacking and wire bonding, inwhich:

[0041]FIG. 17 is a side view of an offset stacked multiple die devicehaving forwardly offset dice connected to a substrate, in accordancewith the invention;

[0042]FIG. 18 is a side view of another embodiment of an offset stackedmultiple die device having forwardly offset dice connected to asubstrate, in accordance with the invention;

[0043]FIG. 19 is a side view of an offset stacked multiple die devicehaving one rearwardly offset die and two forwardly offset dice connectedto a substrate, in accordance with the invention;

[0044]FIG. 20 is a side view of another embodiment of an offset stackedmultiple die device having one rearwardly offset die and two forwardlyoffset dice connected to a substrate, in accordance with the invention;

[0045]FIG. 21 is a side view of an offset stacked multiple die devicehaving two rearwardly offset dice and one forwardly offset die connectedto a substrate, in accordance with the invention;

[0046]FIG. 22 is a side view of another embodiment of an offset stackedmultiple die device having two rearwardly offset dice and one forwardlyoffset die connected to a substrate, in accordance with the invention;

[0047]FIG. 23 is a side view of an offset stacked multiple die devicehaving four dice with alternating forward and rearward offset, connectedto a substrate, in accordance with the invention;

[0048]FIG. 24 is a side view of another embodiment of an offset stackedmultiple die device having four dice with alternating forward andrearward offset, connected to a substrate, in accordance with theinvention;

[0049]FIG. 25 is a side view of another embodiment of an offset stackedmultiple die device having four dice which are sequentially rotated andoffset in at least one direction;

[0050]FIG. 26 is a plan view of an embodiment of an offset stackedmultiple die device having four dice which are sequentially rotated andoffset in at least one direction, in accordance with the invention;

[0051]FIG. 27 is an isometric view of an offset stacked multiple diedevice formed of two dice with bond pads along two adjacent edgeswherein an upper die is offset from an underlying die along both theX-axis and Y-axis in accordance with the invention;

[0052]FIG. 28 is a side view of an offset stacked multiple die deviceformed of four elongate dice which have bond pads along two opposingedges wherein dice are arranged in an alternating sequence providing anoffset from all dice, in accordance with the invention; and

[0053]FIG. 29 is a plan view of an offset stacked multiple die deviceformed of four elongate dice which have bond pads along two opposingedges wherein dice are arranged in an alternating sequence providing anoffset from all dice, in accordance with the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] A new stacked multiple chip device formed of a plurality ofoffset Z-stacked, i.e. vertically-stacked semiconductor dice, togetherwith a method of production thereof, are provided by the invention. Somedevices of the invention may be classified as stacked multi-chip modules(MCM). Semiconductor dice which are particularly usefully stacked inthis construction are those having conductive bond pads along one edge,or alternatively along two adjacent edges of the active surface. Inaddition, a particular embodiment will be described which utilizeselongate i.e. semiconductor dice having bond pads along opposing distaledges of a non-square elongate active surface. Although the device isparticularly adapted to dice of the same surface dimensions and similarbond pad layout, a stack of dice may be formed in accordance with thisinvention which includes one or more semiconductor dice of a differingconfiguration at either end of the stack, or interposed therein. Thestack of semiconductor dice is physically attached to a substrate, inwhich the substrate may comprise for example a printed circuit board(PCB), a memory card, a lead frame, tape automated bonding (TAB) tape orother substrate. Additionally, similar shaped dummy die of silicon andthe like may be used as spacers between semiconductor die in the stack.

[0055] In the figures and this description, semiconductor dice and anyspacers in general will be denoted by the numeral 60, and a lettersuffix i.e. A, B, C, etc. will be used to identify a particularsemiconductor die or spacer or the like of a stack. Numerals identifyingbond pads, bond wires, etc. which relate to a particular semiconductordie will carry the same suffix.

[0056] In this description, bond wires will be described as beingconnected between a semiconductor die and a substrate. It is to beunderstood that the wires are bonded to bond pads on the semiconductordie and to conductive members such as metallization or a lead framewhich may constitute all or part of the substrate. The device may alsoinclude semiconductor die-to-semiconductor die bonds.

[0057] With reference to the drawings of drawing FIGS. 12, 13 and 14,which describe an embodiment of the instant invention, a semiconductordevice 50 having a multi-chip module (MCM) type of configurationcomprises two semiconductor dice 60A and 60B as a stack 61. Thisconfiguration is particularly appropriate to flash memory packages inwhich the die circuits are connected in parallel. In this configuration,the semiconductor dice 60A, 60B have essentially identical circuits, andhave upwardly facing active surfaces 52A, 52B with bond pads 54A, 54Balong one edge 56A, 56B of each active surface, respectively. The bondpads of each semiconductor die are collectively designated as a “field”55 of bond pads. Each semiconductor die 60A, 60B has a length dimension104 and a width dimension 106 which may be equal or unequal therebymaking the die 60A, 60B have different physical sizes and shapes.

[0058] Semiconductor die 60A is shown attached to a substrate 70 byadhesive layer 78. The adhesive layer 78 may be any adhesive capable ofbonding a reverse surface 72 of a die 60 to the active surface 52 ofanother semiconductor die or to a topside 66 of a substrate 70.Semiconductor die 60B is stacked on top of semiconductor die 60A andjoined to it by thin adhesive layer 78. Semiconductor die 60B is offsetfrom semiconductor die 60A along Y-axis 76 a distance 82 which exposesthe field 55 of bond pads 54A. The offset distance 82 may be theshortest distance which permits reliable use of a wire bonding tool, notshown, to bond conductors such as bond wires 62 to the bond pads 54A.Thus, bond pads 54A, 54B are joined by fine metal bond wires 62 or otherconductive members to conductive e.g. metallization areas 58 on thetopside 66 of substrate 70. If so dictated by the design of the device50, certain bond pads 54A and 54B may also be conductively connected toeach other, i.e. on the same semiconductor die 60A or 60B, or fromsemiconductor die 60A to semiconductor die 60B.

[0059] In these figures, the substrate 70 is pictured as a circuit boardor memory card substrate or multimedia card substrate for example. Thisexample is shown with solder balls 64 on its reverse side 68 althoughother configurations of electrical connections may be used.

[0060] A controlled thickness thermoplastic or other type of adhesivemay be used in adhesive layers 78 to join the semiconductor dice 60A and60B to each other, and semiconductor die 60A to the substrate 70.

[0061] The bond pads 54A and 54B of dice 60A and 60B, respectively, arejoined to metallization or other conductors 58 on the substrate 70 bythin bond wires 62. Typically, the bond wires have a diameter of about0.001 inch, and are formed of a metal such as aluminum or gold, oralloys thereof. The preferred method of bonding the wires 62 to the bondpads is known as ultrasonic ball bonding, which forms a low-loop wirebond which is less than the Z-dimension of a semiconductor die 60.Likewise, in a preferred method, ultrasonic “wedge” bonds of wire areformed at the substrate metallization 58.

[0062] In general, semiconductor devices are encapsulated in aprotective package to protect the die surfaces, metallization and wiresfrom damage. As depicted in drawing FIGS. 12 through 14, edges of anexemplary equiangular encapsulating enclosure are defined by lines 84.The encapsulant material may be a polymer, ceramic or other protectivematerial. As shown, the completed i.e. packaged device 50 may be formedto have a low profile vertical (Z) dimension 86 (excluding solder balls64) which is less than prior stacked device heights, because thickintervening layers of adhesive are not required between adjacentsemiconductor dice 60.

[0063] A stack 61 of two or more offset semiconductor dice 60 may alsobe formed on a lead frame 94, as depicted in an example in drawing FIG.12A. The lead frame 94 is typically formed from a material such ascopper, copper alloys, iron-nickel alloys, or the like. Other materials,such as TAB tape, could be used in accordance with this invention aswell. The lead frame 94 is shown with opposing runners 96, a centralpaddle 98, and leads 102 to which wires are attached. The lead frame 94has alignment mechanisms 100 such as precisely positioned marks orholes, for precise positioning of the lead frame during operations suchas die bonding and wire bonding where alignment is critical. In thisexample, semiconductor die 60A is attached to a paddle 98 of lead frame94 with a thin adhesive layer, not shown. The paddle 98 serves as asubstrate to support the stack 61. Semiconductor die 60B is thenattached to overlie a major portion of semiconductor die 60A, whereinthe die edge 56B along which bond pads 54 are positioned is offset adistance 82 from the die edge 56A of the lower semiconductor die 60A, toexpose the bond pads. As shown, conductive bond wires 62A are connectedfrom bond pads 56A of semiconductor die 60A to appropriate leads 102A.Likewise, bond wires 62B are connected from bond pads 56B to leads 102B.Alternatively, TAB bonding or other bonding methods may be used. Asillustrated in drawing FIG. 12B, the semiconductor die 60B is of smallersize than that of semiconductor die 60A. Further, as illustrated indrawing FIG. 12C, the semiconductor die 60B is of larger size thansemiconductor die 60A having three sides of the semiconductor die 60Boverhanging the semiconductor die 60A.

[0064] In the embodiment of drawing FIGS. 12 through 14, both of thesemiconductor dice 60A, 60B have their bond pads 54A, 54B oriented inthe same direction so that they are connected by wires 62 tometallization areas 58 on the same side of the device 50. However, thesemiconductor die orientation and other factors, such as semiconductordie having different sizes and dimensions, may be changed to suit aparticular application. Thus, major design factors affecting the stackedoffset multiple semiconductor die device 50 include the number ofsemiconductor dice 60 in the stack 61, die dimensions, number of dieedges 56 along which bond pads 54 are arrayed, offset direction(s),offset distance 82 and rotation angle of each semiconductor die relativeto the semiconductor die just below.

[0065] As shown in drawing FIG. 15, semiconductor die 60B has beenrotated 180 degrees about central Z-axis 88 such that its edge 56B alongwhich bond pads 54B are positioned is opposite in direction to edge 56Aof semiconductor die 60A. It is evident that semiconductor die 60B mayalternatively be rotated zero degrees, 90 degrees, 180 degrees or 270degrees relative to die semiconductor 60A. The conductive metallization58 on the substrate 70 must be configured for providing short bond wireconnections with the bond pads 54A, 54B.

[0066] Depicted in drawing FIG. 16 is an offset stacked 2-semiconductordie device 50 in which the upper semiconductor die 60B is rotated 90degrees clockwise about Z-axis 88. Thus, the row(s) of bond pads 54B arerotated 90 degrees from the row(s) of bond pads 54A. In this embodiment,both semiconductor dice 60A, 60B are depicted as having active surfaces26 which are substantially square but the device 50 may be formed ofsubstantially non-square semiconductor dice.

[0067] As will be evident, a variety of offset stacking configurationsis available when using semiconductor dice 60 with bond pads 54 alongone edge 56. Depicted in drawing FIGS. 17 through 24 is a variety ofsuch configurations; this application is not limited to these particularconfigurations, which serve as examples. Each of these figures relatesto a stack 61 of four offset semiconductor dice 60A, 60B, 60C and 60D inwhich individual semiconductor die may be offset in a forward directioni.e. to the right, or in a reverse direction i.e. to the left. Inaddition, an individual semiconductor die 60 may be rotated 180 degreesso that the bond pad location is reversed relative to the underlyingsemiconductor die. Reversal of a semiconductor die 60 results inattachment of its bond pads 54 to substrate 70 in a different location.

[0068] For the sake of clarity, drawing FIGS. 17 through 24 do not showadhesive layers, encapsulating material or other details of the device50. The number of semiconductor dice 60 comprising the stack 61 islimited only by design, construction and operational limitations such asmaterials strength, heat generation and dissipation, electricoperability and the like. The design of the stack 61 must be coordinatedwith substrate design i.e. to ensure accurate and rapid wire bonding andmeet other design criteria.

[0069] As shown in drawing FIG. 17, a plurality of semiconductor dice60A, 60B, 60C and 60D may be consecutively stacked in a single offsetdirection, denoted herein as a “forward” direction. All of thesemiconductor dice have bond pads 54 facing in the same direction. Inthis stacking configuration, the bond wires 62A, 62B, 62C or 62D of eachsemiconductor die is bonded to a substrate 70 at the same side of thestack 61.

[0070] The embodiment of drawing FIG. 18 differs from drawing FIG. 17 inthat the uppermost semiconductor die 60D is rotated 180 degrees relativeto the other semiconductor dice, and has bond pads 54D attached to thesubstrate 70 on the other side of the stack 61.

[0071] Illustrated in drawing FIGS. 19 through 24 are other offsetmultiple semiconductor die devices 50 in which semiconductor dice 60 areoffset in both forward and reverse directions.

[0072] Illustrated in drawing FIGS. 19 and 20 are devices 50 which havea second semiconductor die 60B with a reverse offset and which isrotated 180 degrees relative to lowermost semiconductor die 60A.Semiconductor dice 60C and 60D are similarly rotated relative tosemiconductor die 60A, and each is forwardly offset from its underlyingdie. In drawing FIG. 19, the bond wires 62 from the three uppersemiconductor dice 60B, 60C and 60D are bonded to the substrate 70 onthe same side of the stack 61, while semiconductor die 60A is bonded onthe opposing side of the stack. In drawing FIG. 20, semiconductor die60D is attached to the stack 61 in an unrotated position relative to die60A. Semiconductor die 60D has its bond wires 62D connected to substrate14 in the vicinity of bond wires 62A, i.e. on the opposite side of thestack from bond wires 62B and 62C.

[0073] As illustrated in drawing FIGS. 21 and 22, semiconductor dice 60Band 60C are offset in a reverse direction from semiconductor die 60A,and semiconductor die 60D is offset in a positive direction fromunderlying die 60C. Illustrated in drawing FIG. 21, semiconductor dice60C and 60D are both rotated 180 degrees relative to semiconductor dice60A and 60B, so that their bond pads 54C and 54D face in an oppositedirection from bond pads 54A and 54B. Illustrated in drawing FIG. 22,semiconductor die 60D of the device 50 in drawing FIG. 21 has beenrotated 180 degrees and it's bond wires 62D attached to the substrate 14in the vicinity of bond wires 62A and 62B.

[0074] As shown in drawing FIG. 23, the semiconductor dice 60 in stack61 may be ordered in an alternating fashion with respect to both dierotation, i.e. between a forward and reverse direction, and offsetdirection.

[0075] Alternatively, as shown in drawing FIG. 24, the uppermostsemiconductor die 60D of a stack may have the same alternating offsetpattern as the device 50 of drawing FIG. 23, but be rotated to have thesame rotational orientation as its underlying semiconductor die 60C. Thebond wires 62D will be joined to the substrate 70 in the vicinity ofbond wires 62A and 62C.

[0076] Where the bond pads 54 of a die 60 are overhung by a portion ofanother semiconductor die, those bond pads may be wire-bonded to thesubstrate 70 prior to mounting the overhanging die in the stack 61.Using the configuration illustrated in drawing FIG. 19 as an example, itis seen that bond pads 54A are overhung by a portion of semiconductordie 60C. The height 92 of wire loop 90 is less than the die thickness36, enabling wire bonding without subsequent contact of bond wires 62with the overhanging semiconductor die 60C or intervening semiconductordie 60B or silicon spacer 60B.

[0077] Turning now to drawing FIGS. 25 and 26, another embodiment of anoffset stacked device 50 is shown with a stack 61 of four semiconductordice 60A, 60B, 60C and 60D. Each semiconductor die 60 has a squareactive surface 52 and all semiconductor dice are constructed to bephysically identical. By rotating each semiconductor die 60 to be 90degrees from the next lower die, and offsetting each successivesemiconductor die to avoid the bond pads 54 of the next lowersemiconductor die, all bond pads of the four semiconductor dice areexposed for wire bonding in a single uninterrupted step.

[0078] The stacked offset multiple die device 50 of this invention mayhave any form of substrate 70 known in the art. For example, thesubstrate 70 may be a metallized lead frame as already shown in drawingFIG. 12A.

[0079] Turning now to drawing FIG. 27, yet another embodiment of anoffset stacked device 50 of the invention is shown which is formed oftwo or more semiconductor dice such as semiconductor dice 60A, 60Bhaving conductive bond pads 54A and 54B, respectively. The twosemiconductor dice are joined together and to substrate 70 by thinadhesive layers 78. On each semiconductor die, the bond pads are shownas formed along two adjacent edges of the semiconductor die. Thus, forexample, semiconductor die 60A has bond pads 54AA formed along die edge56AA, and bond pads 54AB formed along adjacent die edge 56AB. Likewise,semiconductor die 60B has bond pads 54BA formed along die edge 56BB.

[0080] As shown in drawing FIG. 27, die 60B is offset in position in twodirections. Thus, semiconductor die 60B is offset from semiconductor die60A a distance 82A along the X-axis 74 and a distance 82B along theY-axis 76, whereby all of the bond pads 54AA and 54AB of semiconductordie 60A are exposed for easy wire bonding.

[0081] Additional semiconductor dice 60 may be mounted atopsemiconductor die 60B. These semiconductor dice may be mounted in thesame sequence, using a substrate 70 configured with metallization on twosides only of the stack 61. Alternatively, subsequent semiconductor dice60C, . . . may be mounted atop semiconductor die 60B having the samepattern of offset, i.e. along both the X-axis 74 and Y-axis 76, butrotated 180 degrees relative to semiconductor dice 60A and 60B. As aresult, wire bonds will be made to the substrate 70 on four sides ofstack 61.

[0082] A further embodiment of the invention is illustrated in drawingFIGS. 28 and 29, in which a semiconductor die stack 61 is formed ofsemiconductor dice 60 having bond pads 54 on each of two opposed edges56 of the semiconductor die's active surface 52. In this configuration,each added semiconductor die 60 is rotated 90 degrees or 270 degreesfrom the underlying semiconductor die to place the semiconductor die inan offset position. Each semiconductor die 60 has a length dimension 104which is longer than a width dimension 106 by at least two times therequired offset i.e. to expose the bond pads 54 of the underlyingsemiconductor die. If desired, the semiconductor dice 60 can be of anyconvenient physical size and be of different physical size than theother. Use of more than two semiconductor dice 60 in the stack 61results in semiconductor die pads 54 being overhung by a semiconductordie which is two positions higher in the stack. The manufacturingprocess will require intermediate wire bonding operations in this case.The stack configuration results in wire bonds 62A and 62C tometallization areas 58 of the substrate 70 on two opposing sides of thestack 61, and wire bonds 62B and 62D on the other two opposing sides ofthe stack. Thus, wire bonds are located on all four sides of the stack61.

[0083] As described herein, the invention provides a stacked multiplesemiconductor die device or package of higher electronic density, inwhich individual die of similar size, different size, or the same sizeare offset from each other in the stack, enabling electrical attachmente.g. wire bonding between the semiconductor dice and a substrate. Thus,the overall height of the stack of semiconductor dice, and the packageformed therefrom, is minimal. Multiples of the stacked multiple diepackage may be combined in a large mass storage flash memory apparatusfor example.

[0084] The various embodiments of stacked offset multiple semiconductordie devices which are shown and described herein are exemplary and notlimiting. It is understood that other configurations may includeadditional elements, for example, such elements including additionalsemiconductor dice and lead frames, heatsinks, dielectric layers,packaging, etc., as known in the art.

[0085] It is apparent to those skilled in the art that various changesand modifications may be made in the packaging methods and products ofthe invention as disclosed herein without departing from the spirit andscope of the invention as defined in the following claims.

What is claimed is:
 1. A stacked multiple-semiconductor die device,comprising: a substrate having a surface; at least one conductive bondarea on the surface of the substrate; a plurality of semiconductor dicehaving similar dimensions, each semiconductor die having a activesurface including at least four edges, and a backside; a field ofconductive bond pads disposed on the active surface of eachsemiconductor die, the field of conductive pads positioned along lessthan three edges of the active surface of the semiconductor die, thebackside of a first semiconductor die being attached to the substratesurface adjacent the conductive bond areas of said substrate surface andthe backside of a second semiconductor die is attached to the activesurface of the first semiconductor die in an offset position having thebond pad field of the first semiconductor die being exposed; conductorsconnecting bond pads of the first semiconductor die to conductive bondareas of the substrate; and conductors connecting bond pads of thesecond semiconductor die to one of conductive bond areas of thesubstrate and conductive bond pads of the first semiconductor die. 2.The stacked multiple-semiconductor die device of claim 1, wherein saidplurality of semiconductor dice comprise a stack of semiconductor dicehaving one of substantially the same dimensions and differentdimensions.
 3. The stacked multiple-semiconductor die device of claim 1,comprising at least one additional semiconductor die having a backsideattached to at least a portion of the active surface of the next lowersemiconductor die in an offset position, the bond pad field of eachsemiconductor die being exposed for attachment of said conductorsthereto.
 4. The multiple-semiconductor die stacked device of claim 1,wherein said first semiconductor die is attached to said substrate by athin adhesive layer and said second die is attached to said first die bya thin adhesive layer.
 5. The stacked multiple-semiconductor die deviceof claim 1, wherein each semiconductor die has a field of bond padsalong one edge thereof, and the second semiconductor die being offsetfrom the first semiconductor die in one direction to expose the bondpads of the first semiconductor die for establishing connections fromthe bond pads to the substrate.
 6. The stacked multiple-semiconductordie device of claim 5, further comprising at least one additionalsemiconductor die fixed in a stack to said second semiconductor die,each additional semiconductor die offset from its underlyingsemiconductor die, each semiconductor die being offset in the samedirection from its underlying semiconductor die.
 7. The stackedmultiple-semiconductor die device of claim 6, wherein at least one ofsaid semiconductor dice is rotated one of 90, 180, and 270 degreesrelative to its underlying semiconductor die.
 8. The stackedmultiple-semiconductor die device of claim 6, wherein said at least onerotated semiconductor die is an uppermost semiconductor die.
 9. Themultiple-semiconductor die device of claim 6, wherein said at least onerotated semiconductor die is intermediate the first semiconductor dieand the uppermost semiconductor die.
 10. The stacked multiple-die deviceof claim 5, further comprising at least one additional semiconductor diefixed in a stack to said second semiconductor die, each additionalsemiconductor die offset from its underlying semiconductor die, at leastone of the second semiconductor die and the third semiconductor diebeing rotated 180 degrees relative to said first semiconductor die. 11.The stacked multiple-semiconductor die device of claim 10, wherein eachsemiconductor die is rotated 180 degrees from its underlyingsemiconductor die and offset in a reverse direction thereto.
 12. Thestacked multiple-semiconductor die device of claim 5, further comprisingat least one additional semiconductor die fixed in a stack to saidsecond semiconductor die, each additional semiconductor die offset fromits underlying semiconductor die, the second semiconductor die and eachsubsequent semiconductor die being rotated 90 degrees from itssemiconductor underlying semiconductor die to position bond pads on atleast three sides of the stack.
 13. The stacked multiple-semiconductordie device of claim 5, wherein each semiconductor die has a field ofbond pads along two adjacent edges thereof, and each of the secondsemiconductor die and subsequent semiconductor die being offset from itsunderlying semiconductor die in two directions exposing the bond padsthereof for conductive bonding.
 14. The stacked multiple-semiconductordie device of claim 13, wherein each semiconductor die is offset in thesame two directions relative to its underlying semiconductor die. 15.The stacked multiple-die device of claim 13, wherein at least onesemiconductor die is rotated 180 degrees from its underlyingsemiconductor die.
 16. The stacked multiple-die device of claim 15,wherein at least one rotated semiconductor die includes a topmostsemiconductor die.
 17. The stacked multiple-semiconductor die device ofclaim 5, wherein each semiconductor die has a length greater than awidth whereby rotation of one semiconductor die relative to anunderlying adjacent semiconductor die offsets said first semiconductordie to expose the field of bond pads on said at least one field of bondpads for attaching conductors thereto.
 18. The sackedmultiple-semiconductor die device of claim 1, comprising: a lowersemiconductor die having a field of bond pads positioned thereon forattachment to conductive wires with loops; an upper semiconductor dieoverhanging said field of bond pads by a first height; and anintervening semiconductor die having an upper surface bonded to saidupper semiconductor die with an adhesive layer and a lower surfacebonded to said lower semiconductor die with an adhesive layer, saidintervening semiconductor die offset from said lower and uppersemiconductor dice, the height of overhang between said lowersemiconductor die and upper semiconductor die being substantially equalto the thickness of said intervening semiconductor die and two saidadhesive layers and said height of overhang exceeding the height of bondwire loops attached to said bond pads of the lower semiconductor die.19. The high density multiple die stacked device according to claim 18,wherein the intervening semiconductor die includes one of a piece ofsilicon and an inoperative semiconductor die and an operativesemiconductor die.
 20. The high density multiple die stacked deviceaccording to claim 1, in which said substrate comprises one of a circuitboard, circuit card, lead frame and tape automated bonding (TAB) tape.21. A multiple die stacked device, comprising: a substrate havingconductive areas thereon; a plurality of semiconductor dice attached ina stack, said stack comprising a first semiconductor die attached to thesubstrate and subsequent semiconductor dice attached thereto to formsaid stack, the semiconductor die of the plurality of semiconductor dicein said stack being substantially identical, and the physicalorientation of each of said second and subsequent semiconductor diebeing offset in at least one direction from its underlying semiconductordie and is rotated in one of 0, 90, 180 and 270 degrees relative to saidunderlying semiconductor die to expose bond pads of the underlyingsemiconductor die while minimizing the size of the device.
 22. A highdensity stacked multiple-die device, comprising: a substrate having asurface; conductive bond areas on the surface of the substrate; aplurality of semiconductor dice having substantially the samedimensions, each semiconductor die having a rectangular active surfacehaving at least four edges, and a backside; a field of conductive bondpads disposed on the active surface of each semiconductor die, the fieldpositioned along less than three edges thereof, the backside of a firstsemiconductor die being attached to the substrate surface adjacent theconductive bond areas of said substrate surface, the backside of asecond semiconductor die being attached to the active surface of thefirst semiconductor die in an offset position having the bond pad fieldof the first die is exposed; conductors connecting bond pads of thefirst semiconductor die to conductive bond areas of the substrate; andconductors connecting bond pads of the second semiconductor die to oneof conductive bond areas of the substrate and conductive bond pads ofthe first semiconductor die.
 23. The high density stacked multiple-diedevice of claim 22, wherein said plurality of semiconductor dicecomprise a stack of semiconductor die, each semiconductor die being oneof substantially the same size and of different size.
 24. The highdensity stacked multiple-die device of claim 22, comprising at least oneadditional semiconductor die having a backside attached to the activesurface of the next lower semiconductor die in an offset position, thebond pad field of each semiconductor die exposed for attachment of saidconductors thereto.
 25. The high density multiple die stacked device ofclaim 22, wherein said first semiconductor die is attached to saidsubstrate by a thin adhesive layer and said second semiconductor die isattached to said first semiconductor die by a thin adhesive layer. 26.The high density stacked multiple-die device of claim 22, wherein eachsemiconductor die has a field of bond pads along one edge thereof, andthe second semiconductor die is offset from the first semiconductor diein one direction to expose the bond pads of the first semiconductor diefor establishing connections from the bond pads to the substrate. 27.The high density stacked multiple-die device of claim 26, furthercomprising at least one additional semiconductor die fixed in a stack tosaid second semiconductor die, each additional semiconductor die offsetfrom its underlying semiconductor die, wherein each semiconductor die isoffset in the same direction from its underlying semiconductor die. 28.The high density stacked multiple-die device of claim 27, wherein atleast one of said semiconductor dice is rotated one of 90, 180, and 270degrees relative to its underlying semiconductor die.
 29. The highdensity stacked multiple-die device of claim 28, wherein said at leastone rotated semiconductor die is an uppermost semiconductor die.
 30. Thehigh density stacked multiple-die device of claim 28, wherein said atleast one rotated semiconductor die is intermediate the firstsemiconductor die and the uppermost semiconductor die.
 31. The highdensity stacked multiple-die device of claim 26, further comprising atleast one additional semiconductor die fixed in a stack to said secondsemiconductor die, each additional semiconductor die offset from itsunderlying die, wherein at least one of the second semiconductor die andthe third semiconductor die is rotated 180 degrees relative to saidfirst semiconductor die.
 32. The high density stacked multiple-diedevice of claim 31, wherein each semiconductor die is rotated 180degrees from its underlying die and offset in a reverse directionthereto.
 33. The high density stacked multiple-die device of claim 26,further comprising at least one additional semiconductor die fixed in astack to said second semiconductor die, each additional semiconductordie offset from its underlying semiconductor die, wherein the second dieand each subsequent die is rotated 90 degrees from its underlyingsemiconductor die to position bond pads on at least three sides of thestack.
 34. The high density stacked multiple-die device of claim 26,wherein each semiconductor die has a field of bond pads along twoadjacent edges thereof, and each of the second and subsequentsemiconductor die is offset from its underlying semiconductor die in twodirections exposing the bond pads thereof for conductive bonding. 35.The high density stacked multiple-die device of claim 34, wherein eachsemiconductor die is offset in the same two directions relative to itsunderlying semiconductor die.
 36. The high density stacked multiple-diedevice of claim 34, wherein at least one semiconductor die is rotated180 degrees from its underlying semiconductor die.
 37. The high densitystacked multiple-die device of claim 36, wherein at least one rotatedsemiconductor die includes a topmost semiconductor die.
 38. The highdensity stacked multiple-die device of claim 26, wherein eachsemiconductor die has a length greater than a width whereby rotation ofone semiconductor die relative to an underlying adjacent semiconductordie offsets said first semiconductor die to expose the field of bondpads on said at least one field of bond pads for attaching conductorsthereto.
 39. The high density stacked multiple-die device of claim 22,comprising: a lower semiconductor die having a field of bond padspositioned thereon for attachment to conductive wires with loops; anupper semiconductor die overhanging said field of bond pads by a firstheight; and an intervening semiconductor die having an upper surfacebonded to said upper semiconductor die with an adhesive layer and alower surface bonded to said lower semiconductor die with an adhesivelayer, said intervening semiconductor die offset from said lowersemiconductor die and upper semiconductor die, the height of overhangbetween said lower semiconductor die and upper semiconductor diesubstantially equals the thickness of said intervening semiconductor dieand two said adhesive layers and said height of overhang exceeds theheight of bond wire loops attached to said bond pads of the lowersemiconductor die.
 40. The high density multiple die stacked deviceaccording to claim 22, in which said substrate comprises one of acircuit board, circuit card, lead frame and tape automated bonding (TAB)tape.
 41. A high density multiple die stacked device, comprising: asubstrate having conductive areas thereon; and a plurality ofsemiconductor dice attached in a stack, said stack comprising a firstsemiconductor die attached to the substrate and subsequent dice attachedthereto to form said stack, the semiconductor dice in said stack beingsimilar, and the physical orientation of each of said secondsemiconductor die and subsequent semiconductor dice being offset in atleast one direction from its underlying semiconductor die and rotated inone of 0, 90, 180 and 270 degrees relative to said underlyingsemiconductor die exposing bond pads of the underlying semiconductor diewhile minimizing the size of the device.
 42. The high density multipledie stacked device of claim 41, wherein one of the semiconductor dieincludes one of a piece of silicon and an inoperative semiconductor dieand an operative semiconductor die.
 43. The high density multiple diestacked device of claim 41, wherein one of the semiconductor dieincludes a piece of silicon.
 44. The high density multiple die stackeddevice of claim 41, wherein the semiconductor die are attached to eachother using an adhesive having a thickness of about less than 100microns.
 45. A multiple-semiconductor die device, comprising: asubstrate having a surface; at least one conductive bond area on thesurface of the substrate; a plurality of semiconductor dice, eachsemiconductor die having one of similar dimensions and differentdimensions, each semiconductor die having a active surface including atleast four edges, and a backside; a field of conductive bond padsdisposed on the active surface of each semiconductor die, the field ofconductive pads positioned along less than three edges of the activesurface of the semiconductor die, the backside of a first semiconductordie being attached to the substrate surface adjacent the conductive bondareas of said substrate surface and the backside of a secondsemiconductor die is attached to the active surface of the firstsemiconductor die in an offset position having the bond pad field of thefirst semiconductor die being exposed; conductors connecting bond padsof the first semiconductor die to conductive bond areas of thesubstrate; and conductors connecting bond pads of the secondsemiconductor die to one of conductive bond areas of the substrate andconductive bond pads of the first semiconductor die.
 46. The stackedmultiple-semiconductor die device of claim 45, wherein said plurality ofsemiconductor dice comprise a stack of semiconductor dice having one ofsubstantially different dimensions.
 47. The stackedmultiple-semiconductor die device of claim 45, comprising at least oneadditional semiconductor die having a backside attached to at least aportion of the active surface of the next lower semiconductor die in anoffset position, the bond pad field of each semiconductor die beingexposed for attachment of said conductors thereto.
 48. The stackedmultiple-semiconductor die device of claim 45, wherein eachsemiconductor die has a field of bond pads along one edge thereof, andthe second semiconductor die being offset from the first semiconductordie in one direction to expose the bond pads of the first semiconductordie for establishing connections from the bond pads to the substrate.49. The stacked multiple-semiconductor die device of claim 48, furthercomprising at least one additional semiconductor die fixed in a stack tosaid second semiconductor die, each additional semiconductor die offsetfrom its underlying semiconductor die, each semiconductor die beingoffset in the same direction from its underlying semiconductor die. 50.The stacked multiple-semiconductor die device of claim 49, wherein atleast one of said semiconductor dice is rotated one of 90, 180, and 270degrees relative to its underlying semiconductor die.
 51. The stackedmultiple-die device of claim 49, further comprising at least oneadditional semiconductor die fixed in a stack to said secondsemiconductor die, each additional semiconductor die offset from itsunderlying semiconductor die, at least one of the second semiconductordie and the third semiconductor die being rotated 180 degrees relativeto said first semiconductor die.
 52. The stacked multiple-semiconductordie device of claim 51, wherein each semiconductor die is rotated 180degrees from its underlying semiconductor die and offset in a reversedirection thereto.
 53. The stacked multiple-semiconductor die device ofclaim 49, further comprising at least one additional semiconductor diefixed in a stack to said second semiconductor die, each additionalsemiconductor die offset from its underlying semiconductor die, thesecond semiconductor die and each subsequent semiconductor die beingrotated 90 degrees from its semiconductor underlying semiconductor dieto position bond pads on at least three sides of the stack.
 54. Thestacked multiple-semiconductor die device of claim 49, wherein eachsemiconductor die has a field of bond pads along two adjacent edgesthereof, and each of the second semiconductor die and subsequentsemiconductor die being offset from its underlying semiconductor die intwo directions exposing the bond pads thereof for conductive bonding.55. The stacked multiple-semiconductor die device of claim 54, whereineach semiconductor die is offset in the same two directions relative toits underlying semiconductor die.
 56. The stacked multiple-die device ofclaim 54, wherein at least one semiconductor die is rotated 180 degreesfrom its underlying semiconductor die.
 57. The stacked multiple-diedevice of claim 56, wherein at least one rotated semiconductor dieincludes a topmost semiconductor die.
 58. The stackedmultiple-semiconductor die device of claim 49, wherein eachsemiconductor die has a length greater than a width whereby rotation ofone semiconductor die relative to an underlying adjacent semiconductordie offsets said first semiconductor die to expose the field of bondpads on said at least one field of bond pads for attaching conductorsthereto.
 59. The sacked multiple-semiconductor die device of claim 45,comprising: a lower semiconductor die having a field of bond padspositioned thereon for attachment to conductive wires with loops; anupper semiconductor die overhanging said field of bond pads by a firstheight; and an intervening semiconductor die having an upper surfacebonded to said upper semiconductor die with an adhesive layer and alower surface bonded to said lower semiconductor die with an adhesivelayer, said intervening semiconductor die offset from said lower andupper semiconductor dice, the height of overhang between said lowersemiconductor die and upper semiconductor die being substantially equalto the thickness of said intervening semiconductor die and two saidadhesive layers and said height of overhang exceeding the height of bondwire loops attached to said bond pads of the lower semiconductor die.60. The high density multiple die stacked device according to claim 59,wherein the intervening semiconductor die includes one of a piece ofsilicon and an inoperative semiconductor die and an operativesemiconductor die.
 61. The high density multiple die stacked deviceaccording to claim 45, in which said substrate comprises one of acircuit board, circuit card, lead frame and tape automated bonding (TAB)tape.
 62. A multiple die stacked device, comprising: a substrate havingconductive areas thereon; a plurality of semiconductor dice attached ina stack, said stack comprising a first semiconductor die attached to thesubstrate and subsequent semiconductor dice attached thereto to formsaid stack, the semiconductor die of the plurality of semiconductor dicein said stack being substantially different, and the physicalorientation of each of said second and subsequent semiconductor diebeing offset in at least one direction from its underlying semiconductordie and is rotated in one of 0, 90, 180 and 270 degrees relative to saidunderlying semiconductor die to expose bond pads of the underlyingsemiconductor die while minimizing the size of the device.
 63. A highdensity stacked multiple-die device, comprising: a substrate having asurface; conductive bond areas on the surface of the substrate; aplurality of semiconductor dice having substantially differentdimensions, each semiconductor die having a rectangular active surfacehaving at least four edges, and a backside; a field of conductive bondpads disposed on the active surface of each semiconductor die, the fieldpositioned along less than three edges thereof, the backside of a firstsemiconductor die being attached to the substrate surface adjacent theconductive bond areas of said substrate surface, the backside of asecond semiconductor die being attached to the active surface of thefirst semiconductor die in an offset position having the bond pad fieldof the first die is exposed; p1 conductors connecting bond pads of thefirst semiconductor die to conductive bond areas of the substrate; andconductors connecting bond pads of the second semiconductor die to oneof conductive bond areas of the substrate and conductive bond pads ofthe first semiconductor die.
 64. The high density stacked multiple-diedevice of claim 63, wherein said plurality of semiconductor dicecomprise a stack of semiconductor die, each semiconductor die being oneof substantially the same size and of different size.
 65. The highdensity stacked multiple-die device of claim 63, comprising at least oneadditional semiconductor die having a backside attached to the activesurface of the next lower semiconductor die in an offset position, thebond pad field of each semiconductor die exposed for attachment of saidconductors thereto.
 66. The high density stacked multiple-die device ofclaim 63, wherein each semiconductor die has a field of bond pads alongone edge thereof, and the second semiconductor die is offset from thefirst semiconductor die in one direction to expose the bond pads of thefirst semiconductor die for establishing connections from the bond padsto the substrate.
 67. The high density stacked multiple-die device ofclaim 66, further comprising at least one additional semiconductor diefixed in a stack to said second semiconductor die, each additionalsemiconductor die offset from its underlying semiconductor die, whereineach semiconductor die is offset in the same direction from itsunderlying semiconductor die.
 68. The high density stacked multiple-diedevice of claim 67, wherein at least one of said semiconductor dice isrotated one of 90, 180, and 270 degrees relative to its underlyingsemiconductor die.
 69. The high density stacked multiple-die device ofclaim 68, wherein said at least one rotated semiconductor die is anuppermost semiconductor die.
 70. The high density stacked multiple-diedevice of claim 68, wherein said at least one rotated semiconductor dieis intermediate the first semiconductor die and the uppermostsemiconductor die.
 71. The high density stacked multiple-die device ofclaim 66, further comprising at least one additional semiconductor diefixed in a stack to said second semiconductor die, each additionalsemiconductor die offset from its underlying die, wherein at least oneof the second semiconductor die and the third semiconductor die isrotated 180 degrees relative to said first semiconductor die.
 72. Thehigh density stacked multiple-die device of claim 71, wherein eachsemiconductor die is rotated 180 degrees from its underlying die andoffset in a reverse direction thereto.
 73. The high density stackedmultiple-die device of claim 66, further comprising at least oneadditional semiconductor die fixed in a stack to said secondsemiconductor die, each additional semiconductor die offset from itsunderlying semiconductor die, wherein the second die and each subsequentdie is rotated 90 degrees from its underlying semiconductor die toposition bond pads on at least three sides of the stack.
 74. The highdensity stacked multiple-die device of claim 66, wherein eachsemiconductor die has a field of bond pads along two adjacent edgesthereof, and each of the second and subsequent semiconductor die isoffset from its underlying semiconductor die in two directions exposingthe bond pads thereof for conductive bonding.
 75. The high densitystacked multiple-die device of claim 74, wherein each semiconductor dieis offset in the same two directions relative to its underlyingsemiconductor die.
 76. The high density stacked multiple-die device ofclaim 74, wherein at least one semiconductor die is rotated 180 degreesfrom its underlying semiconductor die.
 77. The high density stackedmultiple-die device of claim 76, wherein at least one rotatedsemiconductor die includes a topmost semiconductor die.
 78. The highdensity stacked multiple-die device of claim 66, wherein eachsemiconductor die has a length greater than a width whereby rotation ofone semiconductor die relative to an underlying adjacent semiconductordie offsets said first semiconductor die to expose the field of bondpads on said at least one field of bond pads for attaching conductorsthereto.
 79. The high density stacked multiple-die device of claim 63,comprising: a lower semiconductor die having a field of bond padspositioned thereon for attachment to conductive wires with loops; anupper semiconductor die overhanging said field of bond pads by a firstheight; and an intervening semiconductor die having an upper surfacebonded to said upper semiconductor die with an adhesive layer and alower surface bonded to said lower semiconductor die with an adhesivelayer, said intervening semiconductor die offset from said lowersemiconductor die and upper semiconductor die, the height of overhangbetween said lower semiconductor die and upper semiconductor diesubstantially equals the thickness of said intervening semiconductor dieand two said adhesive layers and said height of overhang exceeds theheight of bond wire loops attached to said bond pads of the lowersemiconductor die.
 80. The high density multiple die stacked deviceaccording to claim 63, in which said substrate comprises one of acircuit board, circuit card, lead frame and tape automated bonding (TAB)tape.
 81. A high density multiple die stacked device, comprising: asubstrate having conductive areas thereon; and a plurality ofsemiconductor dice attached in a stack, said stack comprising a firstsemiconductor die attached to the substrate and subsequent dice attachedthereto to form said stack, the semiconductor dice in said stack havingat least two different sizes of semiconductor die, and the physicalorientation of each of said second semiconductor die and subsequentsemiconductor dice being offset in at least one direction from itsunderlying semiconductor die and rotated in one of 0, 90 , 180 and 270degrees relative to said underlying semiconductor die exposing bond padsof the underlying semiconductor die while minimizing the size of thedevice.
 82. The high density multiple die stacked device of claim 81,wherein one of the semiconductor die includes one of a piece of siliconand an inoperative semiconductor die and an operative semiconductor die.83. The high density multiple die stacked device of claim 81, whereinone of the semiconductor die includes a piece of silicon.
 84. The highdensity multiple die stacked device of claim 81, wherein thesemiconductor die are attached to each other using an adhesive having athickness of about less than 100 microns.
 85. A high density multipledie stacked device, comprising: a substrate having conductive areasthereon; and a plurality of semiconductor dice attached in a stack, saidstack comprising a first semiconductor die attached to the substrate andsubsequent dice attached thereto to form said stack, the semiconductordice in said stack having at least two different sizes of semiconductordie, the size of the bottom semiconductor die in the stack being smallerin at least one dimension of length, width, and thickness than acorresponding dimension of at least one other semiconductor die in thestack, and the physical orientation of each of said second semiconductordie and subsequent semiconductor dice being offset in at least onedirection from its underlying semiconductor die and rotated in one of 0,90, 180 and 270 degrees relative to said underlying semiconductor dieexposing bond pads of the underlying semiconductor die while minimizingthe size of the device.
 86. The high density multiple die stacked deviceof claim 85, wherein one of the semiconductor die includes one of apiece of silicon and an inoperative semiconductor die and an operativesemiconductor die.
 87. The high density multiple die stacked device ofclaim 85, wherein one of the semiconductor die includes a piece ofsilicon.
 88. The high density multiple die stacked device of claim 85,wherein the semiconductor die are attached to each other using anadhesive having a thickness of about less than 100 microns.
 89. The highdensity multiple die stacked device of claim 85, wherein at least twodimensions of the bottom semiconductor die of length, width, andthickness are smaller in at least one dimension of length, width, andthickness than a corresponding dimension of at least one othersemiconductor die in the stack
 90. A high density multiple die stackeddevice, comprising: a substrate having conductive areas thereon; and aplurality of semiconductor dice attached in a stack, said stackcomprising a first semiconductor die attached to the substrate andsubsequent dice attached thereto to form said stack, the semiconductordice in said stack having at least two different sizes of semiconductordie, the size of the semiconductor die on the bottom of the stack havingat least one dimension of one of length, width, and thickness which islarger than a corresponding dimension of at least another semiconductordie in the stack, and the physical orientation of each of said secondsemiconductor die and subsequent semiconductor dice being offset in atleast one direction from its underlying semiconductor die and rotated inone of 0, 90, 180 and 270 degrees relative to said underlyingsemiconductor die exposing bond pads of the underlying semiconductor diewhile minimizing the size of the device.
 91. The high density multipledie stacked device of claim 90, wherein one of the semiconductor dieincludes one of a piece of silicon and an inoperative semiconductor dieand an operative semiconductor die.
 92. The high density multiple diestacked device of claim 90, wherein one of the semiconductor dieincludes a piece of silicon.
 93. The high density multiple die stackeddevice of claim 90, wherein the semiconductor die are attached to eachother using an adhesive having a thickness of about less than 100microns.
 94. The high density multiple die stacked device of claim 90,wherein at least two dimensions of the bottom semiconductor die oflength, width, and thickness are larger in at least one dimension oflength, width, and thickness than a corresponding dimension of at leastone other semiconductor die in the stack